The integrated circuit industry is under continuous pressure to reduce the size of the components on integrated circuits and to increase the number of devices that can be integrated onto a single chip. These market forces have been associated with what is known in the industry as Moore's Law. Moore's Law suggests that the number of transistors that can be fabricated on an integrated circuit doubles approximately every 18 to 20 months. Although Moore's Law is based upon purely empirical and historical data, it has been proven to be a reliable indicator of trends in the integrated circuit industry.
These market forces have led many in the industry to develop what is known as a System on a Chip (“SOC”). In a System on a Chip, multiple processors, memory circuits, registers, and other components are integrated onto a single computer chip so that one chip can perform the functions of an entire system. Digital Signal Processing (“DSP”) chips commonly have multiple processors on a single chip to simultaneously perform a variety of math-intensive functions. As is known in the art, a memory cache often accompanies each processor on a chip. This memory cache enables the processor to operate at maximum efficiency by reducing the time required to retrieve data from memory locations outside of the chip. The memory cache associated with a processor is commonly an array of Static Random Access Memory (“SRAM”) devices.
Because memory devices utilize very small features, one problem associated with the fabrication of these devices is that they are easily subject to damage from particles, lithographic misalignment, scratches, and other fabrication errors. To address these problems, memory arrays are often built with redundant rows and redundant columns that can be activated to replace rows or columns with defects. During the fabrication process, a memory array will generally be tested and the redundant rows and arrays will be activated before the device is packaged and shipped. If it is determined that the memory array cannot be repaired, then the device is scrapped before costly and time-consuming back-end processes (i.e. packaging) are performed.
A process for testing and repairing a memory array in a cache associated with a single computer processor is described in U.S. patent application Ser. No. 10/136,818 entitled “processor-Based System and Method for Testing Embedded Memory,” which was filed on Apr. 30, 2002 and is hereby incorporated by reference into the specification of this application. To reduce the testing time for the memory associated with a processor core on a single computer chip, the process described in this application loads a computer program designed for execution on the processor on the chip. The program tests the memory cache and generates a repair solution for activating one or more of the redundant rows or columns in the memory array. After the repair solution is generated, it is offloaded from the computer chip so that a laser fusing or electrical fusing process can implement the repair solution. Although this process works well for a single core (i.e. processor) chip, its implementation on a multiple-core chip becomes much more complicated. As a result, there is a need in the art for a method and apparatus for testing memory arrays associated with multiple computer processors on a single chip.